Job In Mumbai > for-job-in-mumbai-shree-placement_q16380825.html
 
for job in mumbai Shree Placement
 http://www.shreeplacementservices.com
Posted on : 2011-10-19 01:00:16
Job ID: 16380825
 
Experience :  ( 7 - 12 yrs.)
Location :  Bengaluru/Bangalore
Education Qualification :  UG - B.Tech/B.E. - Electrical, Electronics/Telecom
Industry Type :  Semiconductors
Key Skills :  A
Job Type : 
Annual Salary :  NA
 
 Job Summary

 
 Job Description
  Job Responsibilities:   Responsible for Field Application Engineer (FAE) activities in the Design for Test (DFT) Domain From a technical stand-point, understanding customer needs on DFT, involve and work with their projects for using right methodologies and tools for successful project completion Involve and drive the Tool evaluation/benchmark; Technical product presentations; Methodology review; Tool deployment and adoption; Provide support to customers during critical Project implementation phases. Work with Technical Account manager and World Wide account teams for forming strategies and successfully driving company tools inside customer projects to enable business success for the company.   Identify and work with potential new groups at customer sites, develop these groups technically for business engagement by way of introduction of new technologies and taking the success at other groups, drive competitive replacement engagement from a technical stand-point Front end Mentor Engagements with customers, and Develop relationships with customer and be a trusted technical advisor to customers. Work with customer support division of company for issue resolution with the help of customer support engineer .   Technical Skills   Should have served roles like Applications Engineer, Synthesis/Scan/DFT implementation Engineer handling medium to high complexity ASICs Work experience in handling test architectures for ASIC, test planning, scan architectures, fault modelling, fault/test coverage/analysis, Test diagnosis, Automatic Test Pattern Generation(ATPG) /Compression, ATPG simulation/debugging, AT-speed testing Work experience in handling Built in Self Test (BIST) techniques for memories and Logic (Memory BIST & Logic BIST), understanding of various Memory test algorithms Experience with Memory compilers, exposure to Memory repair solutions, understanding of verilog and ATPG library models, Understanding and handling Synopsys Design Constraints (SDC) and Static Timing Analysis (STA) Strong working knowledge in EDA tools like TestKompress, MBISTArchitect, DFTAdvisor, Synopsys DFT Compiler, Tetramax, DFTmax, Logic Vision’s BIST tools and other EDA tools in the related domain Scripting skills in TCL/TK/Perl would be desired Foundry exposure to ASIC testing and any experience with ATPG testers, Exposure to Analog DFT, testing special structures like PLLs, SERDES etc., would be an added advantage.
 
 Company Profile
\r\n \r\n A Leading in Job Consltancy\r\n
 
 Contact Details
 
Company Name :  http://www.shreeplacementservices.com
Email :  hrd4@shreeplacementservices.comm
Phone No :  Not Mentioned
Address :  Consultant
Not Mentioned
(@) hrd4@shreeplacementservices.com